DESIGN OF A LOW NOISE, LOW POWER AND SPURIOUS FREE PHASE FREQUENCY DETECTOR AND CHARGE PUMP FOR PHASE-LOCKED LOOPS
Muneeb Abrar1, Shabbir Majeed Chaudhry2
ABSTRACT
This paper presents a very simple approach to design effective PFD (Phase Frequency Detector) and charge pump
(CP)circuitsfor high frequency Phase-Locked Loop (PLL) applications. ThePFD design uses only six transistors for
the detection process, which reduces the chip area and power consumption of the PLL block. It also minimizes the
dead zone and eliminates the reset path to reduce the delay. The output is passed through a buffer to suppress the
distortion and to reduce the overall output noise. Phase noise has been reduced to -156 (dBc/Hz) at 1 MHz offset
frequency. A simple current mirror based charge pump circuit is presented next. The charge pump design incorporates
the use of transmission gates and transistors as capacitors to reduce switching error and clock feed through. The
proposed design has a symmetric structure in terms of W/L ratios,transistor positioning and number of transistors in
both up and down network, which produces a stable charging operation and reduces the spurious jumps in the output
voltage. The overall output noise including thermal and flicker noise of the complete design at high frequencies is
as low as -213 db at 4GHz. The proposed design provides ahigh output voltage swing of 1.4V while operating at
1.5V supply voltage. The design has been implemented in 1P-9M UMC 90nm CMOS technology. Simulations show
the effectiveness of the design in terms of lower power consumption, lower noise and reduced distortion.
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